Demanding AMS Project Design and Tapeout Schedule Met in 22 Days

Multicore Processing Speeds Runtime by 3X, Accelerates Time-to-Quality

Topics include System-Level Design, VMM Verification Methodology and a multi-tool IPL Flow Demonstration

Delivers predictable high compression with only one pair of test data pins

Connectivity IP Leader Continues to Innovate with the DesignWare USB 2.0 picoPHY - The First PHY IP to Support USB 2.0 Battery Charging v1.1 and OTG 2.0 Specifications

Broad DesignWare Audio IP Portfolio Shipped in More Than 100 Million Units

Design-centric yield management enables product engineers to achieve rapid yield ramp and provide cost-effective yield control in volume production

Collaboration Builds on Years of Successful Deployment of Synopsys Verification Solution

Optimized Implementation Methodology Enables 2GHz Fully Synthesizable ARM Cortex-A8 Processor for Advanced Mobile and Consumer Applications

Unique M-Language and Model-Based Solution Delivers Up to 10X Higher Productivity for Communications and Multimedia System Designers

High-Quality DesignWare IP Speeds Time-to-Market for STM32 Connectivity Line of SoCs

Simulation Provides Key Insights in the Design and Optimization of Solar Cells

Eleventh Annual Boston Event is Part of Largest User Conference Program in EDA

In-Design Physical Verification Pivotal in Reducing Time to Tapeout for Advanced Designs

Expands Custom Design Portfolio with Unified Extraction Solution

Accuracy, Performance and Capacity Cited as Key Decision Factors

DesignWare DDR3/2 PHY and Controller IP Address Both Performance and Low Power Enhancements Planned for the DDR3 SDRAM Standard